Reducing series resistance between source and/or drain regions and a channel region
US10388789B2 · kind B2 · utility
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3References
11Claims
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Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Dec 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing series resistance for transistors includes forming a conductive gate over and insulated from a semiconductor substrate, forming source and/or drain extension regions within the substrate and adjacent to respective source and/or drain regions, and forming source and/or drain regions within the substrate. The source and/or drain extension regions are formed from a material alloyed with a first dopant and a second dopant, the first dopant configured to increase a lattice structure of the material forming the source and/or drain extension regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.