Inventor · Albany, NY, US

Mona A. Ebrish

16Patents
2h-index
25Co-inventors
46Inventor score

Filing activity: May 18, 2016 → Jun 17, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US9799736B1 High acceptor level doping in silicon germanium Electricity 398 Active
US10734523B2 Nanosheet substrate to source/drain isolation Performing Operations; Transporting 4 Active
US10361306B2 High acceptor level doping in silicon germanium Electricity 2 Active
US9711507B1 Separate N and P fin etching for reduced CMOS device leakage Electricity 2 Active
US10811528B2 Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs Electricity 2 Active
US9666486B1 Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate Electricity 2 Active
US11031250B2 Semiconductor structures of more uniform thickness Electricity 1 Active
US10229910B2 Separate N and P fin etching for reduced CMOS device leakage Electricity 0 Active
US10381348B2 Structure and method for equal substrate to channel height between N and P fin-FETs Electricity 0 Active
US10361127B1 Vertical transport FET with two or more gate lengths Electricity 0 Active
US10804106B2 High temperature ultra-fast annealed soft mask for semiconductor devices Electricity 0 Active
US11043494B2 Structure and method for equal substrate to channel height between N and P fin-FETs Electricity 0 Active
US10388789B2 Reducing series resistance between source and/or drain regions and a channel region Electricity 0 Active
US10319855B2 Reducing series resistance between source and/or drain regions and a channel region Electricity 0 Active
US10818751B2 Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions Electricity 0 Active
US11569442B2 Dielectric retention and method of forming memory pillar Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.