Handling surface level coherency without reliance on fencing
US10395623B2 · kind B2 · utility
1Cited by
11References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2017 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Aug 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.