Integrated level translator
US10395700B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2018 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Mar 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a circuit structure including: first PMOS and second PMOS each including a gate, source, and drain; wherein sources of first and second PMOS are coupled to first voltage source, gate of first PMOS is cross coupled to drain of second PMOS, gate of second PMOS is cross coupled to drain of first PMOS, drain of the first PMOS is coupled to first bit-line node, and wherein drain of second PMOS is coupled to second bit-line node; write bit-switch having first NMOS coupled to first bit-line node and second NMOS coupled to second bit-line node, wherein first and second NMOS of write bit-switch are respectively coupled to a pair of data nodes each receiving one of a pair of data inputs; and write driver, having a pair of transistor stacks each coupled to between one of the pair of data nodes and ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.