Fully aligned via employing selective metal deposition
US10395986B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2018 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76843
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is presented for creating a fully-aligned via (FAV) by employing selective metal deposition. The method includes forming metal lines within a first inter-layer dielectric (ILD) layer, forming a second ILD layer over the first ILD layer, forming a lithographic stack over the second ILD layer to define areas where via growth is prevented, recessing the lithographic stack to expose a top surface of the metal lines where via growth is permitted by the lithographic stack, and performing metal growth over the exposed top surface of the metal lines where via growth is permitted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.