Uniform electrochemical plating of metal onto arrays of pillars having different lateral densities and related technology
US10396052B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2018 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Jan 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.