Patent · US Active

Semiconductor devices including self-aligned active regions for planar transistor architecture

US10396084B1 · kind B1 · utility

1Cited by

4References

17Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Elliot John Smith · Dresden, DE
Nigel Chan · Sunnyvale, US
Nilesh Kenkare · Dresden, DE
Hongsik Yoon · Daejeon, KR

Key dates

Filing date	Apr 4, 2018
Grant date	Aug 27, 2019
Priority date	—
Expiry date	Apr 4, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10B10/12
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.