Selective gate spacers for semiconductor devices
US10396176B2 · kind B2 · utility
3Cited by
1References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2014 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Sep 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.