Gate cut method
US10396206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2017 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Aug 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/931
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.