Circuit, system and method for thin-film transistor logic gates
US10396796B2 · kind B2 · utility
Inventors
Key dates
| Filing date | May 20, 2016 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | May 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/875
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A unipolar inverter circuit for thin-film transistor circuits including: a driving voltage input; an input signal; a base voltage input; a first stage having a first inverter circuit connected between the driving voltage input and the base voltage input and driven by an input signal; a capacitor coupled to the output of the first stage at a node A; and a second stage having: a second inverter circuit having a second stage load transistor and a second stage driving transistor, wherein a gate of the load transistor is connected to the capacitor at a node B; and a clamping transistor connected between the driving voltage and the node B for controlling a voltage, wherein the clamping transistor gate is connected to the driving voltage input; and an output, wherein the capacitor enables charge injection to the gate of the second stage load transistor to allow approximately full voltage swing at the output based on the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.