Method of fabricating a carrier-less silicon interposer using photo patterned polymer as substrate
US10403510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Dec 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/12042
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.