Source/drain features with an etch stop layer
US10403551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Nov 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0188
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a semiconductor device. The semiconductor device includes a substrate having a first device region and a second device region, a first fin over the substrate in the first device region, a second fin over the substrate in the second device region, a first epitaxial feature over the first fin in the source/drain region of the first fin, a second epitaxial feature over the second fin in the source/drain region of the second fin, and a dielectric layer on the first and second epitaxial features. The first epitaxial feature is doped with a first dopant of a first conductivity and the second epitaxial feature is doped with a second dopant of a second conductivity different from the first conductivity. The dielectric layer is doped with the first dopant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.