Patent · US Active

Molded substrate package in fan-out wafer level package

US10403580B2 · kind B2 · utility

1Cited by

0References

20Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Lizabeth Keser · Chandler, US
Thomas Ort · Veitsbronn, DE
Thomas Wagner · Regelsbach, DE
Bernd Waidhas · Nittendorf, DE

Key dates

Filing date	Dec 29, 2017
Grant date	Sep 3, 2019
Priority date	—
Expiry date	Dec 29, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/18161
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.