Memory device for a dynamic random access memory
US10403627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Oct 10, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed technology relates to a memory device for a dynamic random access memory, or DRAM. In one aspect, the memory device includes a substrate supporting a semiconductor device layer in which a plurality of semiconductor devices are formed. The memory device may further include an interconnection portion formed above the substrate and including a number of metallization levels and dielectric layers, the interconnection portion being adapted to interconnect said semiconductor devices. The memory device may further include a plurality of bit cell stacks arranged in the interconnection portion, each bit cell stack including a plurality of bit cells. Further, such bit cells may include elements such as a charge storage element, a write transistor, and a read transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.