Three-dimensional ferroelectric memory devices
US10403631B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2018 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) ferroelectric memory devices and methods for forming the ferroelectric memory devices are disclosed. In an example, a 3D ferroelectric memory device includes a substrate and a plurality of ferroelectric memory cells each extending vertically above the substrate. Each of the ferroelectric memory cells includes a capacitor and a transistor electrically connected to the capacitor. The capacitor includes a first electrode, a second electrode, and a ferroelectric layer disposed laterally between the first electrode and the second electrode. The transistor includes a channel structure, a gate conductor, and a gate dielectric layer disposed laterally between the channel structure and the gate conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.