Patent · US Active

Handling unaligned load operations in a multi-slice computer processor

US10409598B2 · kind B2 · utility

1Cited by

2References

5Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Sundeep Chadha · Austin, US
Robert A. Cordes · Austin, US
David A. Hrusecky · Johnson City, US
Hung Q. Le · Austin, US
Jentje Leenstra · Nagold, DE
Dung Q. Nguyen · Austin, US
Brian W. Thompto · Austin, US
Albert J. Van Norstrand, Jr. · Round Rock, US

Key dates

Filing date	Jun 21, 2018
Grant date	Sep 10, 2019
Priority date	—
Expiry date	Jun 21, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2213/0042
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.