Interface for memory readout from a memory component in the event of fault
US10409742B2 · kind B2 · utility
7Cited by
15References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2016 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Feb 10, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.