Pre-charging bit lines through charge-sharing
US10410715B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2018 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Feb 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device comprises a plurality of memory cells, a bit line coupled to a first set of the plurality of memory cells at data nodes, and a first voltage supply line coupled to a second set of the plurality of memory cells. The SRAM device further comprises a first switch for selectively coupling the first voltage supply line to a first voltage source to charge the first voltage supply line to a first voltage level and a second switch for selectively coupling the first voltage supply line to the bit line for pre-charging the bit line to a bit line voltage level that is less than the first voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.