Thermal and electromagnetic interference shielding for die embedded in package substrate
US10410971B2 · kind B2 · utility
34Cited by
5References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package that includes an integrated device partially enclosed in a conductive material and embedded in a package substrate. The package includes a package substrate having a first cavity, the integrated device having a first active side and an inactive side embedded in the first cavity, and a structure partially enclosing the integrated device having a first layer and a second layer, wherein the first layer is coupled between the package substrate and the integrated device, and wherein the second layer is disposed over the inactive side of the integrated device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.