Integrated circuits with memory cells and method for producing the same
US10411027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2017 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Oct 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.