Hybrid trigate and nanowire CMOS device architecture
US10411090B2 · kind B2 · utility
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13Claims
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Key dates
| Filing date | Sep 24, 2015 |
| Grant date | Sep 10, 2019 |
| Priority date | — |
| Expiry date | Sep 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.