Patent · US Active

High-voltage transistor device with thick gate insulation layers

US10418380B2 · kind B2 · utility

0Cited by

0References

12Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Elliot John Smith · Dresden, DE
Nigel Chan · Sunnyvale, US
Nilesh Kenkare · Dresden, DE

Key dates

Filing date	Jul 31, 2017
Grant date	Sep 17, 2019
Priority date	—
Expiry date	Dec 7, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/0151
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of forming a semiconductor device is provided including the steps of providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer positioned on the buried insulation layer, and forming a first transistor device, wherein forming the first transistor device includes forming a channel region in the semiconductor bulk substrate and forming a gate insulation layer over the channel region partially of a part of the buried insulation layer and wherein forming the gate insulation layer includes oxidizing a part of the semiconductor layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.