Integrated circuit chip with strained NMOS and PMOS transistors
US10418486B2 · kind B2 · utility
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2References
24Claims
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Key dates
| Filing date | May 10, 2018 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.