Remy BERTHELON
13Patents
1h-index
9Co-inventors
39Inventor score
Filing activity: Dec 22, 2016 → Jun 15, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11411177B2 | Phase-change memory with insulated walls | Electricity | 1 | Active |
| US10263110B2 | Method of forming strained MOS transistors | Electricity | 1 | Active |
| US11690303B2 | Electronic chip with two phase change memories | Electricity | 0 | Active |
| US11723220B2 | Strained transistors and phase change memory | Electricity | 0 | Active |
| US10504897B2 | Integrated circuit comprising balanced cells at the active | Electricity | 0 | Active |
| US12167703B2 | Electronic chip with two phase change memories | Electricity | 0 | Active |
| US11800821B2 | Phase-change memory with an insulating layer on a cavity sidewall | Electricity | 0 | Active |
| US10418486B2 | Integrated circuit chip with strained NMOS and PMOS transistors | Electricity | 0 | Active |
| US10741565B2 | 3D SRAM circuit with double gate transistors with improved layout | Electricity | 0 | Active |
| US10546929B2 | Optimized double-gate transistors and fabricating process | Electricity | 0 | Active |
| US12144187B2 | Strained transistors and phase change memory | Electricity | 0 | Active |
| US10446548B2 | Integrated circuit including balanced cells limiting an active area | Electricity | 0 | Active |
| US10777680B2 | Integrated circuit chip with strained NMOS and PMOS transistors | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.