Non-planar gate all-around device and method of fabrication thereof
US10418487B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2015 |
| Grant date | Sep 17, 2019 |
| Priority date | — |
| Expiry date | Apr 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.