FinFET cut isolation opening revision to compensate for overlay inaccuracy
US10423078B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2019 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Apr 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to address overlay accuracy compensation using finFET cut isolation revisions is disclosed. For an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout: the method determines a number of fins to be cut with same source/drain connection by a fin cut isolation opening, and determines a fin cut isolation pitch in the gate length direction of the plurality of gates. The method revises a size of a fin cut isolation opening in the IC layout based on a number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction. The revision in size of the fin cut isolation compensates for overlay inaccuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.