Apparatuses and methods for memory alignment
US10423353B2 · kind B2 · utility
1Cited by
159References
16Claims
0Family size
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Key dates
| Filing date | Nov 11, 2016 |
| Grant date | Sep 24, 2019 |
| Priority date | — |
| Expiry date | Apr 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes apparatuses and methods related to memory alignment. An example method comprises performing an alignment operation on a first byte-based memory element and a second byte-based memory element such that a padding bit of the first byte-based memory element is logically adjacent to a padding bit of the second byte-based memory element and a data bit of the first byte-based memory element is logically adjacent to a data bit of the second byte-based memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.