John D. Leidel
32Patents
3h-index
11Co-inventors
56Inventor score
Filing activity: Mar 15, 2013 → Nov 13, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9558143B2 | Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device | Physics | 13 | Active |
| US10838865B2 | Stacked memory device system interconnect directory-based cache coherence methodology | Electricity | 6 | Active |
| US9940026B2 | Multidimensional contiguous memory allocation | Physics | 4 | Active |
| US10956439B2 | Data transfer with a bit vector operation device | Electricity | 3 | Active |
| US10007435B2 | Translation lookaside buffer in memory | Physics | 2 | Active |
| US10126947B2 | Interconnect systems and methods using hybrid memory cube links to send packetized data over different endpoints of a data handling device | Physics | 2 | Active |
| US10140104B2 | Target architecture determination | Physics | 1 | Active |
| US10942843B2 | Storing data elements of different lengths in respective adjacent rows or columns according to memory shapes | Physics | 1 | Active |
| US10423353B2 | Apparatuses and methods for memory alignment | Physics | 1 | Active |
| US10884626B2 | Translation lookaside buffer in a switch | Physics | 1 | Active |
| US10430190B2 | Systems and methods for selectively controlling multithreaded execution of executable code segments | Physics | 1 | Active |
| US10540093B2 | Multidimensional contiguous memory allocation | Physics | 0 | Active |
| US9910787B2 | Virtual address table | Physics | 0 | Active |
| US10963398B2 | Virtual register file | Physics | 0 | Active |
| US11782688B2 | Target architecture determination | Physics | 0 | Active |
| US11922148B2 | Systems and methods for application performance profiling and improvement | Physics | 0 | Active |
| US11237808B2 | Target architecture determination | Physics | 0 | Active |
| US11048428B2 | Apparatuses and methods for memory alignment | Physics | 0 | Active |
| US11947798B2 | Packet routing between memory devices and related apparatuses, methods, and memory systems | Physics | 0 | Active |
| US10049054B2 | Virtual register file | Physics | 0 | Active |
| US11693576B2 | Apparatuses and methods for memory alignment | Physics | 0 | Active |
| US11132127B2 | Interconnect systems and methods using memory links to send packetized data between different data handling devices of different memory domains | Physics | 0 | Active |
| US12293105B2 | Apparatuses and methods for memory alignment | Physics | 0 | Active |
| US11741012B2 | Stacked memory device system interconnect directory-based cache coherence methodology | Electricity | 0 | Active |
| US12117929B2 | Memory shapes | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.