Patent · US Active

Systems and methods involving lock-loop circuits, clock signal alignment, phase-averaging feedback clock circuitry

US10425070B2 · kind B2 · utility

24Cited by

4References

10Claims

0Family size

Assignee

GSI Technology Inc. · US

Inventors

Yu-Chi Cheng · Sunnyvale, US
Patrick Chuang · Cupertino, US
Jae Hyeong Kim · 红钢城街道, CN

Key dates

Filing date	Dec 18, 2017
Grant date	Sep 24, 2019
Priority date	—
Expiry date	Dec 18, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K2005/00052
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Systems and methods associated with reducing clock skew are disclosed. In some exemplary embodiments, there is provided circuitry associated with lock loop circuits such as a phase lock loop (PLL). Such circuitry may comprise output clock tree circuitry and phase averaging circuitry. In other exemplary embodiments, there is provided circuitry associated with delay lock loop (DLL) circuits. Such circuitry may comprise output clock tree circuitry and/or phase averaging circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.