Mask shrink layer for high aspect ratio dielectric etch
US10431458B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2016 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Nov 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3205
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.