Semiconductor package and manufacturing method thereof
US10431549B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2018 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Jan 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.