Single instruction multiple data page table walk scheduling at input output memory management unit
US10437736B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Mar 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.