Scheduling events in hardware design language simulation
US10437949B1 · kind B1 · utility
6Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Aug 14, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Simulating a circuit design can include detecting, using a processor, an assignment for a signal of a circuit design during a delta cycle of a simulation of the circuit design and comparing, using the processor, a range of the assignment for the signal with a range of an existing event for the signal for the delta cycle. In response to determining that the range of the assignment for the signal and the range of the existing event meet a condition, the existing event is updated, using the processor, resulting in a merged event. The merged event is scheduled for execution for the delta cycle using the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.