Compact non-volatile memory device of the type with charge trapping in a dielectric interface
US10438960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Dec 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Each memory cell is of the type with charge trapping in a dielectric interface and includes a state transistor selectable by a vertical selection transistor buried in a substrate and comprising a buried selection gate. The columns of memory cells include pairs of twin memory cells. The two selection transistors of a pair of twin memory cells have a common selection gate and the two state transistors of a pair of twin memory cells have a common control gate. The device also includes, for each pair of twin memory cells, a dielectric region situated between the control gate and the substrate and overlapping the common selection gate so as to form on either side of the selection gate the two charge-trapping dielectric interfaces respectively dedicated to the two twin memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.