Metallization layers for semiconductor devices and methods of forming thereof
US10439062B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2016 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Sep 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.