Memory device that communicates error correction results to a host
US10445174B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Dec 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a semiconductor memory unit, a controller configured to communicate with a host through a serial interface and read data stored in a page of the semiconductor memory unit in response to a read command received through the serial interface, and an error-correcting code (ECC) circuit configured to carry out error correction with respect to data read from each unit region of the page. The controller is further configured to transmit, through the serial interface to the host, information that indicates whether or not a number of error bits detected by the ECC circuit in the data read from each unit region of the page through the error correction is greater than a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.