Integrated circuit product having a through-substrate-via (TSV) and a metallization layer that are formed after formation of a semiconductor device
US10446443B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Jan 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.