Mechanically improved microelectronic thermal interface structure for low die stress
US10446466B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 3, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | May 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/8384
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heat dissipation structure for a semiconductor integrated circuit die having a plurality of connection areas may include a thermal mount comprising a plurality of pillars each having an aspect ratio preferable greater than 2:1 and each positioned to connect to one of the connection areas on a peripheral portion of the semiconductor integrated circuit die with one of a plurality of interface layers. A thermal conductivity of materials for the connection areas, the thermal mount, the pillars, each of which is preferably copper, and the interface layers, which are preferably copper nanoparticle layers, has a thermal conductivity greater than 100 Watts per meter degree Kelvin (W/m·K). Flexure of the pillars accommodates mechanical strain arising from temperature changes and differences in coefficients of thermal expansion for materials of the semiconductor integrated circuit die and the thermal mount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.