Integrated circuit including balanced cells limiting an active area
US10446548B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 18, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Oct 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
Abstract
An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and the second nMOS transistors including a channel region made of silicon that is subjected to tensile stress, and their respective gates being positioned at least 250 nm from a border of their active zone; and a third pair including a third nMOS transistor having a same construction as the second nMOS transistor and a third pMOS transistor having a same construction as the first pMOS transistor and having a tensile stress that is lower by at least 250 MPa than the tensile stress of the channel region, respective gates of the transistors of the third pair being positioned at most 200 nm from a border of their active zone.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.