Method for preparing a semiconductor memory structure
US10446556B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Nov 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a method for preparing a semiconductor memory structure. The method includes the following steps: providing a substrate comprising a plurality of active regions extending in a first direction; forming a plurality of first trenches in the substrate, the first trenches comprising a first depth and extending in a second direction different from the first direction; forming a plurality of buried digit lines in the first trenches; forming a plurality of second trenches in the substrate, the second trenches comprising a second depth and extending in a third direction different from the first direction and the second direction; deepening portions of the second trenches to form a plurality of third trenches in the substrate, the third trenches comprising a third depth; and forming a plurality of buried word lines in the third trenches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.