Wei-Ming Liao
32Patents
4h-index
19Co-inventors
56Inventor score
Filing activity: Jan 17, 2008 → Oct 11, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9287271B2 | Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices | Electricity | 10 | Active |
| US8288231B1 | Method of fabricating a recessed channel access transistor device | Electricity | 6 | Active |
| US10763212B1 | Semiconductor structure | Electricity | 4 | Active |
| US11315930B2 | Semiconductor structure and method of manufacturing the same | Electricity | 4 | Active |
| US11101273B1 | Semiconductor structure having word line disposed over portion of an oxide-free dielectric material in the non-active region | Electricity | 4 | Active |
| US10818800B2 | Semiconductor structure and method for preparing the same | Electricity | 3 | Active |
| US10937886B2 | Semiconductor device with negative capacitance material in buried channel | Electricity | 2 | Active |
| US8659079B2 | Transistor device and method for manufacturing the same | Electricity | 2 | Active |
| US10446556B2 | Method for preparing a semiconductor memory structure | Electricity | 1 | Active |
| US10242978B1 | Semiconductor electrostatic discharge protection device | Electricity | 1 | Active |
| US8912065B2 | Method of fabricating semiconductor device | Electricity | 1 | Active |
| US9343547B2 | Method for fabricating a recessed channel access transistor device | Electricity | 1 | Active |
| US10559661B2 | Transistor device and semiconductor layout structure including asymmetrical channel region | Electricity | 1 | Active |
| US10825898B2 | Semiconductor layout structure including asymmetrical channel region | Electricity | 1 | Active |
| US7642142B2 | Method for manufacturing a flash memory device with cavities in upper portions of conductors | Electricity | 0 | Active |
| US10825931B2 | Semiconductor device with undercutted-gate and method of fabricating the same | Electricity | 0 | Active |
| US11482419B2 | Method for preparing transistor device | Electricity | 0 | Active |
| US9368494B2 | Semiconductor device and method of manufacturing the same | Electricity | 0 | Active |
| US10381351B2 | Transistor structure and semiconductor layout structure | Electricity | 0 | Active |
| US11659707B2 | Method of manufacturing a semiconductor structure | Electricity | 0 | Active |
| US11488964B2 | Method of manufacturing semiconductor structure having word line disposed over portion of an oxide-free dielectric material in the non-active region | Electricity | 0 | Active |
| US7956403B2 | Two-bit flash memory | Electricity | 0 | Active |
| US10903080B2 | Transistor device and method for preparing the same | Electricity | 0 | Active |
| US12107002B2 | Manufacturing method of semiconductor structure | Electricity | 0 | Active |
| US10559560B2 | Semiconductor electrostatic discharge protection device | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.