Semiconductor memory device
US10446570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | May 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a peripheral circuit region including a first substrate, a peripheral circuit element disposed at least partially over the first substrate, a first dielectric layer covering the peripheral circuit element and a bottom wiring line disposed in the first dielectric layer and electrically coupled to the peripheral circuit element; a cell region including a second substrate disposed over the first dielectric layer, a memory cell array disposed over the second substrate; a second dielectric layer covering the memory cell array; a contact coupled to the bottom wiring line by passing through the second dielectric layer and the first dielectric layer in a first direction perpendicular to a top surface of the second substrate; and at least one dummy contact disposed adjacent to the contact in the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.