Methods used in forming an array of elevationally-extending strings of memory cells, methods of forming an array of elevationally-extending strings of memory cells, and methods of forming an array of vertical strings of memory cells
US10446578B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Aug 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method used in forming an array of elevationally-extending strings of memory cells comprises forming a lower stack comprising vertically-alternating insulative tiers and wordline tiers. Lower channel openings are in the lower stack. A bridge is epitaxially grown that covers individual of the lower channel openings. A lower void space is beneath individual of the bridges in the individual lower channel openings. An upper stack is formed above the lower stack. The upper stack comprises vertically-alternating insulative tiers and wordline tiers. Upper channel openings are formed into the upper stack to the individual bridges to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. The interconnected channel openings individually have one of the individual bridges there-across. The individual bridges are penetrated through to uncover individual of the lower void spaces. Transistor channel material is formed in an upper portion of the interconnected channel openings elevationally along the vertically-alternating tiers in the upper stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.