Negative capacitance integration through a gate contact
US10446659B2 · kind B2 · utility
1Cited by
1References
16Claims
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Key dates
| Filing date | Oct 13, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Jan 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.