Systems and methods for controlling semiconductor device wear
US10447267B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Aug 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and devices are provided for increasing uniformity of wear in semiconductor devices due to, for example, negative-bias temperature instability (NBTI). The method may include receiving a first NBTI control signal. The method may involve receiving a second NBTI control signal based at least in part on the first NBTI control signal. The method may also involve asserting the first NBTI control signal at a clock input pin of a latch. Further, the method may include asserting the second NBTI control signal at a data input pin of the latch. The method may additionally involve toggling electrical elements downstream of the latch based at least in part on an output of the latch based on the first and second NBTI control signals to increase uniformity of wear on the electrical elements in a default low-power state during NBTI toggling mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.