Redundancy for cache coherence systems
US10452499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Jul 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.