Methods of forming semiconductor device structures including stair step structures
US10453748B2 · kind B2 · utility
4Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2015 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Aug 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.