Molding for large panel fan-out package
US10453764B2 · kind B2 · utility
0Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Aug 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to wafer level packages including one or more semiconductor dies and a method of manufacturing the same. A method comprises: providing a carrier having a predetermined area, disposing a semiconductor device on the predetermined area, and forming a sacrificial wall on a periphery of the predetermined area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.