Multi-row wiring member for semiconductor device and method for manufacturing the same
US10453782B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Nov 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a permanent resist, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the permanent resist with lower faces thereof uncovered in the bottom surface of the permanent resist. The plating layer forming wiring portions is formed on the first plating layer in the permanent resist. The second plating layer is formed in the permanent resist on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the permanent resist. On a bottom-surface side of the permanent resist, a metal frame is formed at the margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.