Method and apparatus for reducing capacitance of input/output pins of memory device
US10453829B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Jun 16, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Jun 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.